STM8 TIM1/TIM2/TIM3 三个16bit定时器可以通过比较模式来实现矩形波的输出.
通过改变比较寄存器CCRxL/CCRxH(x代表第x通道)来改变占空比
配置如下:PWM互补模式输出
|
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 |
void Timer1_init() { //TIM1 capture/compare mode register 1 TIM1_CR1 = 0x00; //disabled TIM1 TIM1_PSCRH = 0x00; TIM1_PSCRL = 0x0F; //分频系数 TIM1_ARRH = 0x00; //频率配置:主时基/分频/频率配置 TIM1_ARRL = 0xE8; TIM1_CCMR1 |= 0x70; //OutputMode PWM TIM1_CCMR2 |= 0x70; //OutputMode PWM TIM1_CCR1H = 0x00; TIM1_CCR1L = 0x54; TIM1_CCR2H = 0x00; TIM1_CCR2L = 0x5E; TIM1_CCER1 |= 0x15; // CH1/CH2/ 关闭互补输出;高电平有效输出高; //TIM1_IER = 0x00; // 不允许产生更新事件中断 TIM1_IER |= 0x01; //允许产生更新事件中断 TIM1_BKR |= 0x80; //刹车寄存器 使能PWM输出 TIM1_DTR = 0x03; //配置死区时间（10*62.5=625ns TIM1_CR1 |= 0x01; //enable Timer 1 } /***** for IAR***/ #pragma vector=TIM1_OVR_UIF_vector __interrupt void TIM1_OVR_UIF(void) { TIM1_SR1 = 0; // 清除更新中断标记，这步不能漏掉，否则会连续进入中断程序 //interrupt } |
TIM1_CR1:
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| ARPE | CMS[1:0] | DIR | OPM | URS | UDIS | CEN | |
| rw | rw | rw | rw | rw | rw | rw | rw |
|
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 |
Bit 7 ARPE: Auto-reload preload enable 0: TIM1_ARR register is not buffered through a preload register. It can be written directly 1: TIM1_ARR register is buffered through a preload register Bits 6:5 CMS[1:0]: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternately. Output compare interrupt flags of channels configured in output (CCiS = 00 in TIM1_CCMRi registers) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternately. Output compare interrupt flags of channels configured in output (CCiS = 00 in CCMRi registers) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternately. Output compare interrupt flags of channels configured in output (CCiS = 00 in TIM1_CCMRi registers) are set both when the counter is counting up and down. Note: It is not allowed to switch from edge-aligned mode to center-aligned mode while the counter is enabled (CEN = 1) Encoder mode (SMS = 001, 010 or 011 in TIM1_SMCR register) must be disabled in centeraligned mode. Bit 4 DIR: Direction 0: Counter used as up-counter 1: Counter used as down-counter Note: This bit is read-only when the timer is configured in center-aligned mode or encoder mode. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the CEN bit) Bit 2 URS: Update request source 0: When enabled by the UDIS bit, the UIF bit is set and an update interrupt request is sent when one of the following events occurs: – Registers are updated (counter overflow/underflow) – UG bit is set by software – Update event is generated through the clock/trigger controller 1: When enabled by the UDIS bit, the UIF bit is set and an update interrupt request is sent only when registers are updated (counter overflow/underflow). Bit 1 UDIS: Update disable. 0: A UEV is generated as soon as a counter overflow occurs, a software update is generated, or a hardware reset is generated by the clock/trigger mode controller. Buffered registers are then loaded with their preload values. 1: A UEV is not generated and shadow registers keep their value (ARR, PSC, CCRi). The counter and the prescaler are re-initialized if the UG bit is set or if a hardware reset is received from the clock/trigger mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock, trigger gated mode, and encoder mode can work only if the CEN bit has been previously set by software. However, trigger mode can set the CEN bit automatically by hardware. |